1. Field of the Invention
The present invention relates to semiconductor memories, and particularly to the equilibration of various nodes associated with a memory array.
2. Description of Related Art
Semiconductor random-access memory devices or sub-systems using arrays of dynamic memory cells (e.g., 1-transistor/1-capacitor (1T/1C) cells) have consistently provided greater density and lower cost per bit than those using static memory cells (e.g., 6-transistor (6T) cells, or 4-transistor/2-resistor (4T/2R) cells). However, such dynamic random-access memory arrays have historically also been lower in performance when compared to static random-access memory arrays. Consequently, system designers have typically chosen dynamic memory arrays (e.g., commercially available dynamic random access memories, or DRAMs) when high density and low cost are required, such as for CPU main memory applications. Conversely, designers have typically chosen static memory arrays when the highest possible performance is required, such as for cache memory and high speed buffer applications. Examples of static memory array devices or sub-systems include commercially available static random access memories (SRAMs) and CPU-resident on-board cache memory sub-systems.
The reasons often cited for the lower performance of dynamic memory arrays include the destructive sensing of all memory cells common to the addressed word line (encountered in virtually all dynamic memory arrays) and the consequential need to restore data back into each sensed memory cell during the active cycle, the need to equilibrate bit lines and various other differential nodes and to precharge various circuit nodes between active cycles, and the requirement for periodic refreshing of all dynamic memory cells.
Traditionally, DRAMs have included a control input, such as RAS, which is asserted to begin an active cycle and deasserted to end the active cycle and cause the DRAM to go back into precharge. In some DRAMs, the transition of the RAS signal itself initiates the activity, while for clocked or synchronous DRAMs, the level of RAS is sampled and strobed into the device on the active edge of the clock, and an active cycle begun when an active RAS level is strobed. During the precharge portion of the memory cycle, one or more internal precharge signals are driven active to accomplish the precharging and equilibration of the various nodes and circuits.
When the next active cycle is initiated, these various precharge/equilibrate signals must be brought inactive before the active cycle can progress significantly. For example, the signal which equilibrates a true bit line to its complement bit line must be brought inactive (e.g., brought low, for an N-channel equilibration device) before a selected word line associated with the bit line pair can be driven active. Because these precharge/equilibrate signals drive such large internal capacitive loads, the signals must be buffered internally by several progressively larger stages to achieve the necessary drive capability to quickly charge and discharge the precharge/equilibrate signals. Because of the delay of these buffers, a significant delay results between the initiating command and the actual buffered precharge/equilibrate signals being driven inactive. Such delays are difficult to overlap with other activities occurring near the beginning of the active cycle without impacting the earliest time that a selected word line may be driven active. Consequently, the access time of a DRAM is increased compared to what might otherwise be achievable.